Inspection of feature patterns produced by litho and etch technology is helpful in order to detect defects in the applied lithographic masks and/or process defects. Inspection tools are based on making comparisons between two dies on a single wafer, or between a die and a reference pattern.
Many chip designs comprise an array of longitudinal features placed parallel to each other at regular distances thereby defining an array with a given pitch. This may be for example an array of fin-shaped structures for making finFET devices on a memory chip. As the size of such features has decreased below the available resolution of immersion lithography, double patterning techniques such as LELE (Litho-Etch Litho-Etch) or SADP (Self-Aligned Double Patterning) have been developed which allow the production of these feature arrays down to the 14 nm technology node. One problem that is typical to these techniques is known as ‘pitch walking’: the pitch of an array of features is not constant between dies printed on the same wafer. For example for a half pitch of 24 nm in the designed pattern, the pitch may change from the center to the edge of the wafer from 24 to 30 nm. Inspection of such dies may lead to a failure to detect small defects because they are masked by the pitch walking error.